1. Technical Field
The present disclosure relates to Phase-to-Digital Converters (PDCs).
2. Background Information
A Phase-Locked Loop (PLL) is a circuit that sees wide applicability in electronics. There are many different types of PLLs. One type of PLL is often referred to as a Digital PLL or a DPLL. A DPLL generally involves a control loop involving a Digitally-Controlled Oscillator (DCO). The DCO outputs a signal whose frequency is a function of a multi-bit digital tuning word on inputs of the DCO. The signal output by the DCO is divided down in frequency by a loop divider of the DPLL to generate a feedback signal. A Phase-to-Digital Converter (PDC) of the DPLL compares the phase of an incoming reference signal to the phase of the feedback signal and outputs a digital phase error word indicative of this phase difference. As the DPLL operates, the PDC outputs a stream of such phase error words. A loop filter filters the stream and outputs a corresponding stream of digital tuning words that are in turn supplied as an input signal to the DCO. When the DPLL is in lock, the DCO is controlled such that the phase of the feedback signal is locked in phase with respect to the phase of the reference signal.
This description of the DPLL is a simplification. For example, during a time before locking of the DPLL, the phase and/or frequency relationship between the reference signal and the feedback signal may be arbitrary. The phase and/or frequency relationship may also be changing in various ways. Similarly, during DPLL operation the phase relationship between the feedback signal and the reference signal may suddenly change for a variety of reasons. Such variations in the phase and frequency relationship between the reference signal and the feedback signal can be seen to disturb PDC operation in undesirable ways. An improved PDC for use in DPLLs is therefore sought.